This invention relates to semiconductor integrated circuits and more particularly to an improvement of the structure of a high speed, large scale semiconductor integrated circuit device.
The conventional signal transmission or conduction in a semiconductor integrated circuit device is carried out with the so-called near end termination in which a termination resistor is connected in the neighbourhood of the output terminal of a circuit of generating the signal, i.e., the termination resistor is connected with the signal generation side terminal of a wiring conductor. This mode of signal transmission increases a propagation delay time in proportion to a square of a wiring conductor length, as is well known. The broken line curve 1 of FIG. 1 illustrates the above-mentioned delay in the signal transmission. The drawing teaches that as the length of the wiring conductor becomes larger, the signal transmission with the near end termination will be very disadvantageous as compared with the signal transmission with the far end termination represented by the broken line curve 2 in which a termination resistor is connected with the receiving side terminal of the wiring conductor. This signal transmission with the far end termination has only been employed in a printed board or the like. The wiring conductor has a resistance r equal to 10 .OMEGA./cm and a capacitance C with respect to the ground equal to 4 pF/cm and undergoes a propagation delay time T.sub.d equal to 66 psec/cm for the far end termination.
Moreover, in order to use the far end termination, the resistance of the wiring conductor must be reduced since a large resistance thereof provides a small amplitude of the signal at the receiving end, which leads to the shortage of margin. The solid lines 3 and 4 in FIG. 1 illustrate a high level signal and a low level signal, varying dependent on the wiring conductor length with the far end termination employed. These high and low level signals are generated by an emitter coupled logic circuit. Thus, with the wiring conductor resistance (r) equal to 10 .OMEGA./cm and the termination resistance equal to 50 .OMEGA., the amplitude of the signal at the receiving end of the wiring conductor 10 cm long. is reduced to 1/2 that at the sending end, which is no longer effective for normal operation of the circuit.
One countermeasure of obviating the reduction of the signal amplitude is proposed in Japanese Patent Application Kokai (Laid-Open) No. 59-4231 (laid-open on Jan. 11, 1984 and corresponding to an earlier Japanese Patent Application No. 57-111730 filed June 30, 1982), for example, in which complementary signals are generated and transmitted or conducted to drive a differential circuit so as to provide a signal with an amplitude effectively doubled. FIG. 2 shows an example of an emitter coupled logic circuit on the basis of the above idea. Namely, two complementary signals (OR output signal 5, NOR output signal 6) in the first circuit on the left side are employed to drive the second circuit on the right side. This circuit structure enables the second circuit to normally operate with the voltage between these two signals as large as about several tens of mV.
Conventionally, however, for such a pair of wiring conductors for conducting the complementary signals in the signal transmission, there has been considered such a structure that above a GaAs substrate (not shown) respective wiring conductors 7 and 8 for transmitting or conducting the complementary two signals lie on the same plane in parallel to powering/grounding layers, i.e., common potential level layers 9, as seen from FIGS. 3a and 3b. This structure is disclosed in the paper by Seki et al "General Meeting S3-3 for The Institute of Electronics and Communication Enginners of Japan pp. 2-331 and 2-332", for example. This structure of wiring conductors provides a weak electromagnetic coupling between the pair of wiring conductors 7 and 8, which result in the inconvenience of large crosstalk between the pair of the above wiring conductors 7 and 8 and another pair of wiring conductors adjacent thereto (not shown). For a multi-layer structure, use of the above-mentioned arrangement of the wiring conductor pairs requires that the powering/growing layers 9 be provided by all means for the purpose of preventing the crosstalk between the upper and lower wiring conductor pairs as shown in FIG. 3B, which gives rise to a problem of the increase of the number of layers.